A High-Speed Class-D Amplifier

Eric Shen and Alec Petridis. ECE 137B, Audio Amplifier Checkoff 3.

The overall goal of this lab is to design for a class-D amplifier with efficiency greater than 60% and a minimum switching speed of 250 kHz. In addition, negative feedback is applied to suppress quantization noise, and phase compensation will be applied to ensure stability of the feedback loop.

Introduction and Statement of Design Goals

For our design, we will be using a FPGA to perform Delta-Sigma modulation on our input audio signal. The modulation frequency will be set to 25 MHz. The FPGA output will be sent to a power amplification stage configured in a half-bridge topology before the quantization noise is filtered out using an LC low-pass filter and the amplified original signal is delivered to the load. While our design differs drastically from the official project description in that we are utilizing a FPGA for Delta-Sigma modulation and a gate driver IC to switch our output power transistors, Permission was obtained from Professor Rodwell to focus our design efforts on maximizing the bandwidth of our circuit, which necessitates the use of ICs and digital components due to the higher parasitics, slower slew rates, and lower reliabilities of discrete analog components.

Switch-Mode Power Amplification Stage

To properly amplify our Delta-Sigma modulation signal output from the FPGA, we will use an LM1210 gate driver IC to drive a pair of EPC2038 N-channel GaN HEMTs in a half-bridge configuration. At a switching frequency of 25 MHz, it is unfeasible to design a gate driver from scratch using discrete components due to wiring parasitics, and therefore an IC must be used. Furthermore, traditional silicon power MOSFETS are unable to operate in this regime due to sluggish rise and fall times. Instead, we chose to use GaN HEMTs due to their higher electron mobility and lower gate capacitance, which allows for faster rise times compared to silicon devices.

To start, the Delta-Sigma modulation signal and its complement are outputted from the FPGA and sent to pins HI_EN and PWM_LI on the LM1210 chip respectively. Those two signals will be amplified internally in the chip and outputted on pins HO and LO to drive the high-side and low-side transistors Q3 and Q4. Capacitors C2, C3, C4, C6, C15, C16, C17, C18, C19, and C20 are power supply bypass capacitors used to create low-impedance paths for AC to flow to ground.

The high-side transistor, Q3, is driven using an additional synchronous bootstrap circuit to ensure its gate voltage sits above the power rail voltage that Q3 is pulling up to, so that its gate-source voltage drop is above threshold during the entire duration of the high cycle. This is achieved using a floating source setup, where the LM1210 internal high-side driver outputs a 5 V swing relative to the source of Q3 rather than ground.

Bootstrap Circuit Analysis

To analyze the operation of the bootstrap circuit, we will first analyze the operation of transistor Q2. To start, we assume an initial steady stage with no input signal into the amplifier. As such, the low side (LO) output of LM1210 is referenced to ground. This forms a potential difference between the LO node and the 5 V supply node connected to D2 and C2. Due to this potential difference, the schotty diodes D2 and D1 are forward biased, and a current flows through D2 to the gate of Q2, then through R1 and the parallel combination of D1 and R1 to the LO node. Under the condition of DC steady state, C1 is fully charged and acts as an open circuit. Since D1 and D2 are BAT54 schotty diodes whose forward voltage depends on current and the voltage across C1 depends on the forward voltage drops of D1 and D2, we will use an iterative method to estimate the forward voltage of D1 and D2.

First, assume D1 and D2 have no voltage drop and are therefore shorts. In this regime, current flows from the 5 V source into R2, then D1 shorts R1 and provides a direct path to ground. Therefore, the current through D1 and D2 is \( I_{D2} = \dfrac{5\,\text{V}}{27\,\text{k}\Omega} = 0.19\,\text{mA} \). From the BAT54 datasheet, this roughly corresponds to a forward voltage drop of 0.24 V. In the second iteration, we assume D1 and D2 have a \( V_f = 0.24\,\text{V} \) and recalculate the current going through them. For D1, current flows from a singular path from the 5 V source through D2 and R2. Therefore, the current through D2 is the same as the current through R2. D2 sets the voltage on one side of R2 to be \( 5\,\text{V} - 0.24\,\text{V} = 4.76\,\text{V} \). D1 sets the voltage on the other side of R2 to be \( 0\,\text{V} + 0.24\,\text{V} = 0.24\,\text{V} \).

Therefore, the current through D2 and R2 is \( I_{D2} = \dfrac{4.76\,\text{V} - 0.24\,\text{V}}{27\,\text{k}\Omega} = 0.17\,\text{mA} \). For D1, the current through D2 and R2 is split into parallel paths between D1 and R1. From KCL, \( I_{D2} = I_{D1} + I_{R1} \). Rearranging, \( I_{D1} = I_{D2} - I_{R1} \). Since the voltage at this node is the forward voltage drop of D1, we calculate the current across it to be \( I_{D1} = 0.17\,\text{mA} - \dfrac{0.24\,\text{V}}{20\,\text{k}\Omega} = 0.16\,\text{mA} \). In this second iteration, the currents through D1 and D2 still correspond to a forward voltage drop of 0.24 V. Therefore, we will use this value as a best estimate. From this, the voltage across C1 is estimated to be \( 4.76\,\text{V} - 0.24\,\text{V} = 4.52\,\text{V} \).

Next, assume the input signal into the amplifier is turned on, so that the output voltage of the LO pin begins to alternate between 0 V and 5 V at a periodic cycle corresponding to the switching frequency of 50 MHz. When LO is high, R1 pulls the voltage at the node where R1, R2, C1, and D1 to 5 V. C1 resists any instantaneous change to the voltage across it and therefore the voltage on the other side of C1, at the gate of Q2 and the cathode of D2 jumps up to \( 5\,\text{V} + V_{C1} = 5\,\text{V} + 4.52\,\text{V} = 9.52\,\text{V} \). This puts D2 into reverse bias and prevents any currents across it. Since the gate of Q2 is now at 9.52 V and the source of Q2 is tied to a 5 V supply, \( V_{gs2} = 9.52\,\text{V} - 5\,\text{V} = 4.52\,\text{V} > V_{th,max} = 2.5\,\text{V} \) and Q2 begins conducting current. In this calculation, we assumed the initial ohmic voltage loss across R1 to be 0 as when D2 is reverse biased, there are no paths for current flow through. R1 therefore acts as a pull-up resistor and C1 acts as a charge pump. However, because there is still a potential difference across R2, C1 will start discharging current back through R2 and R1. C1's discharging time constant can be calculated as \( \tau_{C1} = C_1 (R_1 + R_2) = (22\,\text{nF})(27\,\text{k}\Omega + 20\,\text{k}\Omega) = 1\,\text{ms} \). Even for a 99% duty cycle pulse, its on time is only \( 0.99 \cdot \dfrac{1}{50\,\text{MHz}} = 19.8\,\text{ns} \). Since this is much less than C1's time constant, C1 discharges minimally during LO's high cycle and Q2 stays on. Once LO's output voltage swings low again, the voltage at the gate of Q2 jumps back down to around 4.52 V, putting it back in cutoff. Similarly, D2 becomes forward biased again and C1 is recharged through the 5 V supply. Therefore, we see this charge pump setup ensures that Q2 is only on during the low duty cycle.

During the low duty cycle, the low-side transistor Q4 is on, which pulls the source of Q3 (HS) to ground. Simultaneously, Q2 is also conducting, drawing current from the 5 V supply through R3 to C14 and the cathode of D3. In the schematic, C14 is a 4 terminal feedthrough capacitor, however, only pins 1 and 2 are the traditional connections to its parallel plates, while pins 3 and 4 are used to reduce its equivalent series inductance. If C14 initially have no charge, it will begin charging with a time constant of roughly \( \tau_{C14} = C_{14}\bigl(R_{ds,on,Q2} + R_3 + (R_{ds,on,Q4}\,\|\,R_L)\bigr) = (100\,\text{nF})\bigl(3.3 + 4.7 + (3.3\,\Omega \,\|\, 200\,\Omega)\bigr) = 1.1\,\mu\text{s} \) until it have roughly a 5 V potential across. D3 here is a 5.1 V zener diode in reverse bias placed in parallel with C14 to prevent accidental voltage overshoots from destroying Q3, as the EPC 2038 GaN HEMTs can only handle up to 6 V across its gate and source. While this charging time constant is still much longer than the period of the 50 MHz switching frequency, when the duty cycle is high, Q2 goes into cutoff and the path containing C14 becomes an open circuit. While this prevents C14 from charging during the low cycle, C14 cannot discharge either. Assuming an average duty cycle of 50%, this essentially doubles the time it takes for C14 to fully charge. However, since C14 is connected across the HS and HB node, once it is fully charged, it will maintain a 5 V potential difference between HB and HS. During the high cycle, HS, where the source of the high side transistor Q3 is, is pulled up to 75 V while HB is pulled up to 80 V from this 5 V potential difference. During the high cycle, the output voltage of HO is pulled up to HB from internal push-pull circuitry inside the LMG1210. Since HB is 80 V, and HO is connected to the gate of Q3, this bootstrap configuration allows for a gate-source voltage of 5 V to be maintained during the high cycle, despite the source of Q3 getting pulled all the way up to the positive supply rail. Since the maximum gate-source voltage threshold to ensure the GaN HEMTs are not in cutoff is only 2.5 V, Q3 will conduct for the full duration of the high cycle.

Half-Bridge Output Rise Time

The rise time of the switching waveform outputted by Q3 and Q4 can be estimated using the charge control method using given capacitance values for the EPC 2038 transistors. From its datasheet, \( C_{ISS} = 7\,\text{pF} \), \( C_{RSS} = 0.02\,\text{pF} \), and \( C_{OSS} = 1.4\,\text{pF} \), where \( C_{RSS} = C_{GD} \), \( C_{OSS} = C_{GD} + C_{SD} \), and \( C_{ISS} = C_{GD} + C_{GS} \). Using this, we can solve for the values of individual capacitances connecting the three terminals and obtain \( C_{GD} = 0.02\,\text{pF} \), \( C_{SD} = C_{OSS} - C_{GD} = 1.4\,\text{pF} - 0.02\,\text{pF} = 1.38\,\text{pF} \), and \( C_{GS} = C_{ISS} - C_{GD} = 7\,\text{pF} - 0.02\,\text{pF} = 6.98\,\text{pF} \).

Next, we will split the rise time into the ohmic and constant current regions. Q3/4 will first be in the constant current region, where the output voltage rises linearly. Once the output voltage rises sufficiently, Q3/4 will enter the ohmic region, where the RC charging time constant determines rise time. Given a supply rail of 75 V, a gate-source voltage of 5 V, and a typical threshold voltage of 1.7 V, the drain-source voltage in which Q3/4 enter the ohmic region can be calculated as \( V_{ds} = V_{gs} - V_{th} = 5 - 1.7 = 3.3\,\text{V} \). For a total swing of 75 V, Q3/4 is in the constant current region for a \( \Delta V_{out} = 75\,\text{V} - 3.3\,\text{V} = 71.7\,\text{V} \) and in the ohmic region for a \( \Delta V_{out} = 3.3\,\text{V} \).

We first calculate the rise time in the constant current region. Using the charge control method, the sum of the change in charge on the output can be written as:

From symmetry, the change in voltage across one transistor means the opposite change in voltage across the other. However, since we are only tracking changes, the difference in sign doesn't matter. In addition, the change in \( V_{gd} \) and \( V_{sd} \) as a result of the change in \( V_{out} \) is the exact same as the change in \( V_{out} \), therefore \( \Delta V_{gd} = \Delta V_{sd} = \Delta V_{out} \). This simplifies our sum to

The charging time is given as \( \frac{\Delta Q}{I} \) where \( I \) is estimated to be 500 mA from the datasheet. The rise time in this region is therefore

Moving on to the ohmic region, the rise time is given as a 10-90 risetime with respect to the RC time constant of the system, where the R is simply the on resistance of Q3/4 given as 3.3 ohms. We can therefore solve for the time as

The total rise time is the the rise time of the two regimes combined, which is

Due to the symmetry of the circuit, where both the high-side and the low-side are driven with the same transistor model with the same capacitances as seen from the output node, the rise and fall times of the output stage will be equal.

The fastest switching frequency achievable by this circuit is given by the formula \( f_{clk,max} = \dfrac{0.1}{t_{rise}} = \dfrac{0.1}{0.42\,\text{ns}} = 238\,\text{MHz} \). Since our sampling frequency of 25 MHz falls about a decade below this theoretical maximum switching frequency limit, our design can comfortably operate in this regime.

Output Low-Pass Filter

After amplification, a low-pass filter is placed at the output of the amplifier to remove high-frequency quantization noise. The filter is a simple RLC design consisting of a 33 µH inductor, 680 pF capacitor, and a 200 ohm load. The transfer function of this filter is \( H(s) = \dfrac{1}{s^2 LC + s\frac{L}{R} + 1} \). The natural frequency of this transfer function is given as \( \omega_n = \dfrac{1}{\sqrt{LC}} = \dfrac{1}{\sqrt{(33\,\mu\text{H})(680\,\text{pF})}} = 6.67 \cdot 10^6\ \tfrac{\text{rad}}{\text{s}} \). The damping factor is given as \( \zeta = \dfrac{\omega_n L}{2R} = \dfrac{6.67 \cdot 10^6\,\text{rad/s}\,(33\,\mu\text{H})}{2(200\,\Omega)} = 0.55 \). Since the damping factor is less than 1, this filter will have a -40 db/dec rolloff at a cutoff frequency of \( f_c = \dfrac{\omega_n}{2\pi} = \dfrac{6.67 \cdot 10^6\,\text{rad/}}{2\pi} \approx 1\,\text{MHz} \). The figure below is a plot of the low-pass filter transfer function.

Boost Converter Power Supply

Due to limitations on the supply voltage of the in-lab power supplies, in order supply our power amplification stage with 75 V on the high side, we designed a boost converter circuit to step up an input voltage of 12 V to an output voltage of 75 V.

Our boost converter circuit is driven using an LM3478 controller IC. A 12 V input supply voltage is fed through the VIN pin. The resistor R5 on the FA pin controls the switching frequency outputted by the chip. The formula relating the this resistor to the switching frequency is given on the datasheet as \( R = 4.503 \cdot 10^{11} \cdot f_s^{-1.26} \), rearranging, we can solve for the switching frequency to be \( f_s = \left(\dfrac{105\,\text{k}\Omega}{4.503 \cdot 10^{11}}\right)^{-\frac{1}{1.26}} = 184\,\text{kHz} \). The DR pin connects to the gate of Q1 and outputs a PWM waveform with the 184 kHz switching frequency set by R5. R6 is a current-sensing resistor used as a part of the chip's internal feedback network to protect components against current spikes. The voltage across R6 is pulled into the ISEN pin via R7. If a current above a threshold is detected, the output of the chip shuts down for the remainder of the switching period. C7 and R4 form a compensation network to preventing oscillations and improve phase margins for the chip's error correction network, they are connected to the chip via the COMP pin. C7, C8, C9, C11, C12, and C13 are power supply bypass capacitors. R8, R9, and R10 sets the voltage at the output of the boost converter circuit and R10 is set as a trim potentiometer in order to adjust supply voltage during testing. The voltage divider formed by R8 and R9+R10 is used to feed a portion of the output voltage back into the DR pin and is used to adjust the output voltage through controlling the duty-cycle of the output PWM waveform driving Q1. The equation for the output voltage as a function is given on the datasheet as \( V_{out} = \dfrac{1.26\,\text{V}\,(R_{f1} + R_{f2})}{R_{f2}} \), where \( R_{f1} = R_8 \) and \( R_{f2} = R_9 + R_{10} \). When the potentiometer is tuned to 0 ohms, the output voltage of the boost converter is \( \dfrac{1.26\,\text{V}\,(59\,\text{k}\Omega + 1\,\text{k}\Omega)}{1\,\text{k}\Omega} = 75.6\,\text{V} \). When the potentiometer is tuned to its maximum resistance of 10 kiloohms, the output voltage of the boost converter is \( \dfrac{1.26\,\text{V}\,(59\,\text{k}\Omega + 1\,\text{k}\Omega + 10\,\text{k}\Omega)}{1\,\text{k}\Omega + 10\,\text{k}\Omega} = 8\,\text{V} \). During the duty cycle of Q1, current is drawn through L1 and flows through Q1 and R6 into ground. When the output voltage at the gate of Q1 goes low, Q1 shuts off, severing the path to ground. The inductor L1 pushes back on the change in current and generates a boost in voltage, which forward biases D5 and supplies its stored energy during the charging cycle as current going to the load. The voltage outputted through L1 is dependent on the duty cycle of the PWM waveform and the input voltage, with a higher duty cycle getting a bigger step up in voltage. This relationship is given as \( V_{out} = \dfrac{V_{in}}{1-D} \), for our circuit configuration's maximum voltage output of 75.6 V, the duty cycle of the PWM waveform driving Q1 is \( D = \dfrac{V_{out} - V_{in}}{V_{out}} = \dfrac{75.6\,\text{V} - 12\,\text{V}}{75.6\,\text{V}} = 84\% \).

Delta-Sigma Modulation and Feedback

The 2nd-order delta-sigma modulation was implemented on the FPGA in Verilog as follows:

module dsm_2nd #(
    parameter integer IW = 16,
    parameter integer EW = 22
) (
    input  wire                 clk,
    input  wire                 rst_n,
    input  wire signed [IW-1:0] din,
    output reg                  y_bit,
    // Sim debug taps
    output wire signed [EW-1:0] dbg_v1,
    output wire signed [EW-1:0] dbg_v2
);
    localparam signed [EW-1:0] FS = $signed({1'b0, 1'b1, {(IW-1){1'b0}}}); // +2^(IW-1)

    reg signed [EW-1:0] v1, v2;
    assign dbg_v1 = v1;
    assign dbg_v2 = v2;

    wire signed [EW-1:0] din_e = {{(EW-IW){din[IW-1]}}, din};
    wire signed [EW-1:0] y_fb  = y_bit ? FS : -FS;

    // Compute next state combinationally.
    wire signed [EW-1:0] v1_next = v1 + din_e  - y_fb;
    wire signed [EW-1:0] v2_next = v2 + v1_next - y_fb;
    wire                 y_next  = ~v2_next[EW-1];   // sign bit clear => positive

    always @(posedge clk) begin
        if (!rst_n) begin
            v1    <= 0;
            v2    <= 0;
            y_bit <= 1'b0;
        end else begin
            v1    <= v1_next;
            v2    <= v2_next;
            y_bit <= y_next;
        end
    end
endmodule

To analyze this feedback system, we will first consider the two difference equations that define the two integrators used in the modulator.

First, \( v_1[n] = v_1[n-1] + x[n-1] - y[n-1] \), where \( v_1 \) is the output of the first integrator, \( x \) is the input signal of the system, and \( y \) is the output signal of the system. Taking the z-transform of this equation yields \( V_1(z) = z^{-1}V_1(z) + z^{-1}X(z) - z^{-1}Y(z) \), which rearranges to \( V_1(z) = \dfrac{z^{-1}}{1 - z^{-1}}\bigl[X(z) - Y(z)\bigr] \).

The second integrator is given as \( v_2[n] = v_2[n-1] + v_1[n] - y[n-1] \). Taking the z-transform gives \( V_2(z) = z^{-1}V_2(z) + V_1(z) - z^{-1}Y(z) \), which rearranges to \( V_2(z) = \dfrac{1}{1 - z^{-1}}\bigl[V_1(z) - z^{-1}Y(z)\bigr] \).

The 1-bit quantizer that converts the original input signal into an on/off pulse can be approximated as an adder, where the quantization noise \( e[n] \) is added to the input signal. Writing this in the z-domain, we see that \( Y(z) = V_2(z) + E(z) \). From these three equations, the feedback system can be visualized as the block diagram below.

STF, NTF and Loop Transmission

From the derived equations above and their equivalent block diagram, we can compute the signal transfer function (STF) and the noise transfer function (NTF). We can first substitute the equation for \( V_2 \) into \( V_1 \) to obtain

Combining common terms, this simplifies into

Next, we can substitute this expression for \( V_2 \) into the equation for \( Y \) to obtain

Collecting terms:

The factor \( \left(1 + \dfrac{2z^{-1} - z^{-2}}{(1 - z^{-1})^2}\right) \) simplifies into \( \dfrac{1}{(1 - z^{-1})^2} \), multiplying the equation by this factor yields the final simplified form of

Looking at the contributions to the output \( Y(z) \) from the input signal \( X(z) \) and the quantization noise \( E(z) \), we see that our STF is therefore \( z^{-1} \) and our NTF is \( (1 - z^{-1})^2 \). The STF corresponds to a 1 unit delay between the input and output signal and therefore no attenuation in magnitude. The NTF meanwhile contains a pair of zeros at the origin, therefore its amplitude rises at a rate of 40 dB/dec.

Next, to ensure that the feedback loop is stable, we will compute the loop transmission T(z) and ensure that its magnitude reaches unity gain before its phase shift goes below -180 degrees. To compute the loop transmission, we will force X(z) and E(z) = 0, cut off the feedback network at a point, input a test signal and measure the output at the node right before the loop is completed. This could be represented by the following block diagram below.

We see that by breaking the loop and applying a test signal \( W \) and measuring the output \( W' \), the loop transmission is therefore given as \( T(z) = -\dfrac{W'(z)}{W(z)} \). From this, we see that the output of integrator 1 is just \( -\dfrac{z^{-1}}{1 - z^{-1}}W(z) \). A time-shifted \( W(z) \) then gets subtracted from this signal, so that the input into integrator 2 becomes \( -\dfrac{z^{-1}}{1 - z^{-1}}W(z) - z^{-1}W(z) \). Multiplying this signal by the transfer function of integrator 2 gives \( W'(z) = \left(-\dfrac{z^{-1}}{(1 - z^{-1})^2} - \dfrac{z^{-1}}{(1 - z^{-1})}\right)W(z) \). Applying the formula for the loop transmission, we find that

To check for stability, we first find the frequency for which the magnitude of \( T(z) \) reaches 0 dB or equivalently a gain of 1. We set \( z = e^{j\omega T} \) where T is the sampling period given as \( T = \dfrac{1}{f_s} = \dfrac{1}{25\,\text{MHz}} = 40\,\text{ns} \) and solve for \( f_{loop} \) in the equation \( |T(e^{j2\pi f_{loop}T})| = 1 \), for which we obtain \( f_{loop} = 7.1\,\text{MHz} \). Next, we check the phase of the loop transmission at this frequency, for which we find \( \angle T(e^{j2\pi f_{loop}T}) = -156^\circ \). Since the phase at \( f_{loop} \) is not below -180 degrees, this feedback network is stable with a phase margin of \( -156^\circ - (-180^\circ) = 24^\circ \). The magnitude and phase of the STF, NTF, and the loop transmission T(z) are plotted in the figure below.

We see that around the point where the loop transmission magnitude reaches 0 dB, the magnitude of the NTF also rises above the STF, and the quantization noise is no longer attenuated at all. Since the cutoff frequency of our output low-pass filter is set to 1 MHz and sets the hard limit for the amplifier bandwidth. To see how well the noise is suppressed at the higher end of the circuit bandwidth, the figure below will plot the same three transfer functions but with the x-axis zoomed in to around the LPF cutoff frequency.

We see that at the cutoff frequency of 1 MHz, the quantization noise is only suppressed by about a little more than 20 dB, however, past that point, the LPF takes over and suppresses all frequencies to ensure minimal noise reaches the load.

Signal-to-Noise Ratio

Lastly, we will compute the SNR of the delta-sigma modulator output as a function of frequency, where for a metric of well the noise is suppressed at each frequency, we will apply the formula \( SNR(f) = \dfrac{|STF(e^{j2\pi fT})|^2}{|NTF(e^{j2\pi fT})|^2} \). Since the magnitude of STF is just 1 for all frequencies, we will need to compute the power spectral density of the NTF only.

To convert to decibels, we apply

Using this, we can check the SNR at a low frequency of 1 kHz, the higher end of the audio band at 20 kHz, one decade below the circuit bandwidth at 100 kHz, the circuit cutoff frequency of 1 MHz, and the Nyquist frequency of 12.5 MHz.

Lastly, the figure below plots the SNR as a function of frequency from DC up to the Nyquist rate, and we see that the SNR is well above 0 for the entire circuit bandwidth, and therefore, we can conclude that the quantization noise is well suppressed in the circuit's operating frequency range.

Checkoff Results

Audio Amplifier Checkoff 3, group C4. Eric Shen and Alec Petridis. TA signed, May 29th.